1. Field of the Invention
The invention relates to the field of microelectronics fabrication. More particularly, the invention relates to the fabrication of trenches in silicon substrates employed within microelectronics fabrications.
2. Description of the Related Art
Semiconductor microelectronics fabrications are formed from semiconductor substrates within and upon whose surfaces are formed semiconductor microelectronics devices. The semiconductor microelectronics devices are connected internally and externally to the semiconductor substrates upon which they are formed through use of patterned conductor layers which are separated by dielectric layers.
As semiconductor microelectronics fabrication integration levels have increased and semiconductor microelectronics device and patterned layer dimensions have decreased, it has become more prevalent in the art of semiconductor microelectronics fabrication to employ isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form patterned planarized trench isolation regions within isolation trenches within semiconductor substrates in order to separate active regions of the semiconductor substrates within and upon which are formed semiconductor microelectronics devices.
Such shallow trench isolation (STI) methods are desirable for forming patterned planarized trench isolation regions within isolation trenches within semiconductor substrates employed within semiconductor microelectronics fabrications, since shallow trench isolation (STI) methods typically provide patterned planarized trench isolation regions which are nominally coplanar with the surfaces of adjoining active regions of a semiconductor substrate which they separate. Such nominally co-planar patterned planarized trench isolation regions and adjoining active regions of a semiconductor substrate generally accommodate employing a limited depth of focus of an advanced photoexposure apparatus employed when forming advanced semiconductor microelectronics devices and patterned conductor layers within an advanced semiconductor microelectronics fabrication.
Of the methods which may be employed for forming patterned planarized shallow trench isolation (STI) regions within semiconductor substrates employed within semiconductor microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods employed to fill trenches with dielectric material in conjunction with chemical mechanical polish (CMP) planarization methods have recently received considerable attention. In high density plasma chemical vapor deposition (HDP-CVD) methods, simultaneous chemical vapor deposition (CVD) and inert gas sputtering removal rates are precisely controlled to bring about a net rate of deposition of a layer of silicon oxide dielectric material with desirable properties such as planarity, gap filling, etc. within an isolation trench after its formation within the semiconductor substrate.
While high density plasma chemical vapor deposition (HDP-CVD) methods for trench filling undertaken in conjunction with subsequent chemical mechanical polish (CMP) planarizing methods are thus desirable within the art of semiconductor microelectronics fabrication for forming patterned planarized shallow trench isolation (STI) regions within isolation trenches within semiconductor substrates employed within semiconductor microelectronics fabrications, patterned planarized trench isolation regions so formed and employed are often not entirely without problems. In particular, the formation of the shallow isolation trench itself before filling and planarization can produce difficulties due to the method of selective etching employed to fabricate the trench, especially when the semiconductor substrate employed is a silicon semiconductor substrate as is commonly the case.
In order to form an isolation trench in the semiconductor substrate employed within a semiconductor microelectronics fabrication, an etch resistant layer such as a patterned photoresist etch mask layer is employed, often in conjunction with other etch stop layers, through which is etched the trench pattern by anisotropic subtractive etching of the silicon semiconductor substrate to form the shallow isolation trench. During the etching reactions, it is desirable to form trenches which are free of residues and which have smooth surfaces.
Various methods have ben disclosed for forming shallow isolation trenches within semiconductor substrates employed within microelectronics fabrication.
For example, Leung, in U.S. Pat. No. 4,729,815, discloses a method for forming a vertical walled trench within a semiconductor substrate with rounded top corners and rounded bottom corners. The method employs a three step etching process with CHF.sub.3 and, in part, NF.sub.3 etching gases and a DC bias voltage which is adjusted differently for each of the three steps to provide the vertical walls and the rounded top and rounded bottom corners.
Further, HO et al., in U.S. Pat. No. 5,674,775, disclose a method for forming a trench in a semiconductor substrate with rounded top corners. The method employs a silicon etch buffer layer formed over a silicon substrate and an anisotropic etch to form first a rounded sidewall spacer layer from the buffer layer, and then as etching continues a trench within the silicon substrate with rounded upper corners. The anisotropic etching is performed with Cl.sub.2 and HBr etching gases.
Yet further, Lee et al., in U.S. Pat. No. 5,735,561, disclose a method for forming a shallow trench in a semiconductor substrate with a curved profile. The method employs silicon spacers, temporarily formed on the sides of the trench etching pattern, with rounded profiles formed by anisotropic etching. As the temporary spacer layers are etched away, the curved profile is transferred to the mouth of the trench being etched into the semiconductor substrate. As in the previously cited patent, the etching gases may be Cl.sub.2 and HBr.
Finally, Yu et al., in U.S. Pat. No. 5,801,083, disclose a method for forming a shallow isolation trench in a silicon substrate with rounded corners. The method employs a polymer coating formed upon the trench opening as a temporary mask to permit formation of the trench followed by thermal oxidation of the silicon to convert the corners to a rounded profile.
Desirable in the art of microelectronics fabrication are additional methods for forming within semiconductor substrates shallow trenches with smooth residue free surfaces to reduce defects and asperities which can lead to further problems in fabrication.
It is towards this goal that the present invention is generally and specifically directed.